[<<Previous Entry]
[^^Up^^]
[Next Entry>>]
[Menu]
[About The Guide]
Organization of CMOS Memory - Clock
00h-0Eh is defined by the clock hardware and all must follow it. Other
manufacturers generally follow the same format as specified for the
region 10h - 2Fh. Some also follow the IBM format for 30h-33h but not all
(Zenith in particular is different).
The first fourteen bytes are dedicated to the MC146818 chip clock functions
and consist of ten read/write data registers and four status registers, two
of which are read/write and two of which are read only.
The format of the ten clock data registers (bytes 00h-09h) is:
00h Seconds (BCD 00-59, Hex 00-3B) Note: Bit 7 is read only
01h Second Alarm (BCD 00-59, Hex 00-3B)
02h Minutes (BCD 00-59, Hex 00-3B))
03h Minute Alarm (BCD 00-59, Hex 00-3B)
04h Hours (BCD 00-23, Hex 00-17 if 24 hr mode)
(BCD 01-12, Hex 01-0C if 12 hr am)
(BCD 81-92. Hex 81-8C if 12 hr pm)
05h Hour Alarm (same as hours)
06h Day of Week (01-07 Sunday=1)
07h Date of Month (BCD 01-31, Hex 01-1F)
08h Month (BCD 01-12, Hex 01-0C)
09h Year (BCD 00-99, Hex 00-63)
BCD/Hex selection depends on Bit 2 of register B (0Bh)
12/24 Hr selection depends on Bit 1 of register B (0Bh)
Alarm will trigger when contents of all three Alarm byte registers
match their companions.
The following is the on-chip status register information.
0Ah Status Register A (read/write) (usu 26h)
Bit 7 - (1) time update cycle in progress, data ouputs undefined
(bit 7 is read only)
Bit 6,5,4 - 22 stage divider. 010b - 32.768 Khz time base (default)
Bit 3-0 - Rate selection bits for interrupt.
0000b - none
0011b - 122 microseconds (minimum)
1111b - 500 milliseconds
0110b - 976.562 microseconds (default)
0Bh Status Register B (read/write)
Bit 7 - 1 enables cycle update, 0 disables
Bit 6 - 1 enables periodic interrupt
Bit 5 - 1 enables alarm interrupt
Bit 4 - 1 enables update-ended interrupt
Bit 3 - 1 enables square wave output
Bit 2 - Data Mode - 0: BCD, 1: Binary
Bit 1 - 24/12 hour selection - 1 enables 24 hour mode
Bit 0 - Daylight Savings Enable - 1 enables
0Ch Status Register C (Read only)
Bit 7 - Interrupt request flag - 1 when any or all of bits 6-4 are
1 and appropriate enables (Register B) are set to 1. Generates
IRQ 8 when triggered.
Bit 6 - Periodic Interrupt flag
Bit 5 - Alarm Interrupt flag
Bit 4 - Update-Ended Interrupt Flag
Bit 3-0 ???
0Dh Status Register D (read only)
Bit 7 - Valid RAM - 1 indicates batery power good, 0 if dead or
disconnected.
Bit 6-0 ???
This page created by ng2html v1.05, the Norton guide to HTML conversion utility.
Written by Dave Pearson